Semiconductor devices have been required to have a reduced size and a reduced thickness and to be more inexpensive. To meet these requirements, a BGA (Ball Grid Array) configuration and a CSP (Chip Size Package) configuration use a resin wiring board as a board on which a semiconductor element is mounted.
Such a resin wiring board normally has wiring patterns on the opposite surfaces thereof. The wiring board has, on one of the opposite surfaces, a semiconductor element mounting area in which a semiconductor element is mounted and element connection terminals connected to the wiring patterns. The element connection terminals are arranged in an area inside the semiconductor element mounting area or in an area around the outer periphery of the semiconductor element mounting area. External connection terminals are provided on the other surface of the wiring board.
A solder resist layer is formed on one of the surfaces of the wiring board. The element connection terminals are exposed from the solder resist layer. A solder resist layer is also formed on the other surface of the wiring board. The external connection terminals are exposed from this solder resist layer. The element connection terminals and the external connection terminals are connected together via inner layer conductors, through conductors, or the like formed inside the wiring board.
To meet the requirements for the reduction of the size and thickness of semiconductor devices, very thin resin wiring boards of thickness at most 0.2 mm have been prevailing.
Such a thin resin wiring board is likely to be significantly warped when a semiconductor element is mounted on the wiring board. The warpage of the wiring board may result in inappropriate connections. For example, inappropriate connections are likely to occur when semiconductor element is stacked on another semiconductor element already mounted on the wiring board or when a semiconductor device having a wiring board on which a semiconductor element is mounted is mounted on a mother board or the like.
Thus, Japanese Patent Laid-Open No. 2000-216304 proposes an invention for improving the flatness of a semiconductor device of a BGA configuration using a thin board.
In the invention, a wiring board has a required wiring pattern and a housing hole in which a semiconductor element is housed. The housing hole penetrates the wiring board in the thickness direction thereof. A heat sink is fixed, via a bonding layer, to a back surface of the wiring board which is opposite a mounting surface. The heat sink covers the opening of the housing hole for the semiconductor element.
A solder resist layer is formed on the wiring board so as to cover the mounting surface. A terminal portion of a wiring pattern which forms external connection terminals is exposed from the solder resist layer. The solder resist layer is formed of a photosensitive resist and has a greater thermal expansion coefficient than the wiring board. A resin layer is formed over the solder resist layer, which is made of a resin having a smaller thermal expansion coefficient than the solder resist layer.
The thermal shrinkage of the solder resist layer can be inhibited by setting the thermal expansion coefficient of the solder resist layer greater than that of the wiring board, while setting the thermal expansion coefficient of the resin layer smaller than that of the solder resist layer, as described above. This makes it possible to avoid the possible warpage of the wiring board, allowing a very flat semiconductor device to be implemented.
That is, the above invention forms a first resin layer made of the solder resist layer on only one surface of the wiring board and forms a second resin layer having a smaller thermal expansion coefficient than the solder resist layer on the first resin layer. This improves the flatness of the wiring board.
However, it is expected that the rigidity of the heat sink fixedly bonded to the mounting surface, the other surface of the wiring board, is actually effective in contributing to improving the flatness.
The solder resist layer may be cracked or separated under heat. For example, if a semiconductor device or the like, which is likely to generate heat, is mounted on a printed wiring board with a solder resist layer formed as a surface layer, heat generated by the semiconductor device or during solder bump formation may exert a high stress on the solder resist layer. In some cases, the solder resist layer may be cracked or separated.
To prevent such cracking or separation, Japanese Patent Laid-Open No. 2001-53448 discloses an invention using a solder resist layer containing an inorganic filler.
The invention forms the solder resist layer containing the inorganic filler on the printed wiring board to reduce the thermal expansion coefficient of the solder resist layer. This reduces the difference of the thermal expansion coefficient between the solder resist layer and an interlayer resin insulating layer or the like which is present around the periphery of the solder resist layer.
As a result, after a process of manufacturing a printed wiring board or a process of mounting an electronic part such as a semiconductor element on the printed wiring board, the solder resist layer can be prevented from being cracked or separated. The publication also shows that a solder resist layer of the same material as that described above is formed on both the mounting surface and back surface of the printed wiring board.
That is, in the above invention, the solder resist layer, formed on the surface layer of the printed wiring board, contains the inorganic filler and thus has the small thermal expansion coefficient. This prevents the solder resist layer from being cracked during a heating step such as soldering.
If an insulating resin layer is formed using a photosensitive resin such as a solder resist, and a via hole is formed in the insulating layer made of the insulating resin layer, then the printed wiring board may be significantly warped when the insulating resin layer is dried after the formation of the via hole.
Japanese Patent Laid-Open No. 11-26190 discloses a method for inhibiting the possible warpage of a printed circuit board. The method completely dries and cures solder resist layers formed on the opposite surfaces of the printed wiring board, that is, insulating resin layers, before the formation of a via hole. Thus, during the drying, the resist layers on the opposite surfaces of the printed wiring board have the same area. This equalizes shrinkage behavior on the opposite surfaces of the board, reducing possible warpage.
However, the method requires the use of a laser for a process of forming a via hole in the solder resist layer. This not only increases facility costs but also makes it difficult to form an opening pattern of any shape. In particular, when a die pattern is formed under a semiconductor element, an opening pattern with a relatively large area needs to be formed. It is difficult to process such an opening pattern using a laser.
The present invention solves these problems. An object of the present invention is to provide a wiring board that is minimally warped even if the wiring board made of resin is thin and has wiring patterns of different shapes formed on the opposite surface thereof, as well as a thin, small, and reliable semiconductor device implemented using the wiring board.